brenden
682afacd30
Trimmed monorepo checkout (fluxer_desktop + packages/voice_engine_v2 + tools/ci) with a "Connect to a Different Server" menu item and popout that lets the desktop app switch to any self-hosted Fluxer instance, plus fixes for well-known discovery on single-domain self-hosted deployments and a false-positive ERR_ABORTED on same-origin client redirects during the switch. Defaults to chat.fluxr.chat and uses an isolated userData directory from the official build.
192 lines
6.6 KiB
Rust
192 lines
6.6 KiB
Rust
#![feature(asm)]
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#![allow(
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dead_code,
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non_upper_case_globals,
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unused_macros,
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non_snake_case,
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unused_assignments
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)]
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use std::time::Instant;
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macro_rules! r2 { ($($stat:stmt)*) => { $( $stat )* $( $stat )* } }
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macro_rules! r4 { ($($stat:stmt)*) => { r2!(r2!($($stat)*)) }}
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macro_rules! r8 { ($($stat:stmt)*) => { r4!(r2!($($stat)*)) }}
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macro_rules! r16 { ($($stat:stmt)*) => { r4!(r4!($($stat)*)) }}
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macro_rules! r32 { ($($stat:stmt)*) => { r8!(r4!($($stat)*)) }}
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macro_rules! r64 { ($($stat:stmt)*) => { r8!(r8!($($stat)*)) }}
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macro_rules! r128 { ($($stat:stmt)*) => { r8!(r16!($($stat)*)) }}
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macro_rules! r1024 { ($($stat:stmt)*) => { r8!(r128!($($stat)*)) }}
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macro_rules! r4096 { ($($stat:stmt)*) => { r4!(r1024!($($stat)*)) }}
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const _F32: [f32; 1024] = [12.; 1024];
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const F32: *const f32 = _F32.as_ptr();
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/*
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fn ruin_cache() {
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let _a = (0..1000000).collect::<Vec<i32>>();
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}
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*/
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macro_rules! b {
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($f: block, $inner_loop: expr, $measures: expr) => {{
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let mut values = Vec::with_capacity($measures);
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for _ in 0..$measures {
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// ruin_cache();
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let start = Instant::now();
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for _ in 0..$inner_loop {
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unsafe { $f };
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}
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values.push(start.elapsed());
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}
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values.sort();
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values[$measures / 2].as_nanos() as f64 / 1e9 / $inner_loop as f64
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}};
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}
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fn main() {
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let cycle = b!(
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{
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r1024!(asm!("orr r0, r0, r0", out("r0") _));
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},
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1000,
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1000
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) / 1024.;
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let indep_fmla = b!(
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{
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r8!(asm!("
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vmla.f32 q0, q0, q0
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vmla.f32 q1, q1, q1
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vmla.f32 q2, q2, q2
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vmla.f32 q3, q3, q3
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vmla.f32 q4, q4, q4
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vmla.f32 q5, q5, q5
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vmla.f32 q6, q6, q6
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vmla.f32 q7, q7, q7
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", out("q0") _, out("q1") _, out("q2") _, out("q3") _, out("q4") _, out("q5") _, out("q6") _, out("q7") _));
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},
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1000,
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1000
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) / 64.;
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eprintln!("rcp tp: indep fmla: {}", indep_fmla / cycle);
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let dep_accu_fmla = b!(
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{
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r16!(asm!("
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vmla.f32 q15, q0, q0
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vmla.f32 q15, q1, q1
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vmla.f32 q15, q2, q2
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vmla.f32 q15, q3, q3
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vmla.f32 q15, q4, q4
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vmla.f32 q15, q5, q5
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vmla.f32 q15, q6, q6
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vmla.f32 q15, q7, q7
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vmla.f32 q15, q8, q8
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vmla.f32 q15, q9, q9
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vmla.f32 q15, q10, q10
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vmla.f32 q15, q11, q11
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vmla.f32 q15, q12, q12
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vmla.f32 q15, q13, q13
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vmla.f32 q15, q14, q14
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", out("q0") _, out("q1") _, out("q2") _, out("q3") _, out("q4") _, out("q5") _, out("q6") _, out("q7") _,
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out("q8") _, out("q9") _, out("q10") _, out("q11") _, out("q12") _, out("q13") _, out("q14") _, out("q15") _));
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},
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1000,
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1000
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) / 16.
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/ 15.;
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eprintln!("rcp tp: accu-dep fmla: {}", dep_accu_fmla / cycle);
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let load_s_using_vld1_64 = b!(
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{
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let mut p = F32;
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r16!(asm!("
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vld1.64 {{d0-d3}}, [{0}]!
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vld1.64 {{d4-d7}}, [{0}]!
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vld1.64 {{d8-d11}}, [{0}]!
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vld1.64 {{d12-d15}}, [{0}]!
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vld1.64 {{d16-d19}}, [{0}]!
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vld1.64 {{d20-d23}}, [{0}]!
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vld1.64 {{d24-d27}}, [{0}]!
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vld1.64 {{d28-d31}}, [{0}]!
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",
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inout(reg) p,
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out("q0") _, out("q1") _, out("q2") _, out("q3") _, out("q4") _, out("q5") _, out("q6") _, out("q7") _,
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out("q8") _, out("q9") _, out("q10") _, out("q11") _, out("q12") _, out("q13") _, out("q14") _, out("q15") _));
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},
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1000,
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1000
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) / 16.
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/ 64.; // each line load 8 s
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eprintln!(
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"rcp tp: load s using vld1_64 ia {}",
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load_s_using_vld1_64 / cycle
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);
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let load_s_using_vldm_q = b!(
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{
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let mut p = F32;
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r16!(asm!("
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vldm {0}!, {{q0-q3}}
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vldm {0}!, {{q4-q7}}
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vldm {0}!, {{q8-q11}}
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vldm {0}!, {{q12-q15}}
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",
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inout(reg) p,
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out("q0") _, out("q1") _, out("q2") _, out("q3") _, out("q4") _, out("q5") _, out("q6") _, out("q7") _,
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out("q8") _, out("q9") _, out("q10") _, out("q11") _, out("q12") _, out("q13") _, out("q14") _, out("q15") _));
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},
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1000,
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1000
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) / 16.
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/ 64.;
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eprintln!(
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"rcp tp: load s using vldmia q: {}",
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load_s_using_vldm_q / cycle
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);
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let load = b!(
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{
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let mut p = F32;
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r16!(asm!("
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vldr.64 d0, [{0}]
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vldr.64 d1, [{0}, #8]
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vldr.64 d2, [{0}, #16]
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vldr.64 d3, [{0}, #24]
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vldr.64 d4, [{0}, #32]
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vldr.64 d5, [{0}, #40]
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vldr.64 d6, [{0}, #48]
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vldr.64 d7, [{0}, #56]
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vldr.64 d8, [{0}, #64]
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vldr.64 d9, [{0}, #72]
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vldr.64 d10, [{0}, #80]
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vldr.64 d11, [{0}, #88]
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vldr.64 d12, [{0}, #96]
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vldr.64 d13, [{0}, #104]
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vldr.64 d14, [{0}, #112]
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vldr.64 d15, [{0}, #120]
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vldr.64 d16, [{0}, #128]
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vldr.64 d17, [{0}, #136]
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vldr.64 d18, [{0}, #144]
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vldr.64 d19, [{0}, #152]
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vldr.64 d20, [{0}, #160]
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vldr.64 d21, [{0}, #168]
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vldr.64 d22, [{0}, #176]
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vldr.64 d23, [{0}, #184]
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vldr.64 d24, [{0}, #192]
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vldr.64 d25, [{0}, #200]
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vldr.64 d26, [{0}, #208]
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vldr.64 d27, [{0}, #216]
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vldr.64 d28, [{0}, #224]
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vldr.64 d29, [{0}, #232]
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vldr.64 d30, [{0}, #240]
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vldr.64 d31, [{0}, #248]
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add {0}, #256
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",
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inout(reg) p,
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out("q0") _, out("q1") _, out("q2") _, out("q3") _, out("q4") _, out("q5") _, out("q6") _, out("q7") _,
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out("q8") _, out("q9") _, out("q10") _, out("q11") _, out("q12") _, out("q13") _, out("q14") _, out("q15") _));
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},
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1000,
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1000
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) / 16.
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/ 64.;
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eprintln!("rcp tp: load s using vldr d + imm: {}", load / cycle);
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}
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