Add native self-hosted instance connection to fluxer_desktop
Trimmed monorepo checkout (fluxer_desktop + packages/voice_engine_v2 + tools/ci) with a "Connect to a Different Server" menu item and popout that lets the desktop app switch to any self-hosted Fluxer instance, plus fixes for well-known discovery on single-domain self-hosted deployments and a false-positive ERR_ABORTED on same-origin client redirects during the switch. Defaults to chat.fluxr.chat and uses an isolated userData directory from the official build.
This commit is contained in:
+479
@@ -0,0 +1,479 @@
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// vim: ft=arm
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.arm
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.text
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.global armvfpv2_mmm_f32_4x4_{{suffix}}
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.type armvfpv2_mmm_f32_4x4_{{suffix}}, %function
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// C tile:
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// s16 s20 s24 s28
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// s17 s21 s25 s29
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// s18 s22 s26 s30
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// s19 s23 s27 s31
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// packed A: (2x4) alternating between (s0-s3) and (s4-s7)
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// packed B: (2x4) alternating between (s8-s11) and (s12-15)
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// all vfp registers in use.
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armvfpv2_mmm_f32_4x4_{{suffix}}:
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/*
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pld [r1]
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pld [r1, #8]
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pld [r2]
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pld [r2, #8]
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*/
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push { r4-r12 } // no lr (we're a leaf), no fp. #24 bytes
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ldr r8, [sp, #28]
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ldr r9, [sp, #24]
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// r8=rsc, r9=csc
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vmrs r6, FPSCR
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bic r6, r6, #0x00370000
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vmsr FPSCR, r6
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vpush { s16-s31 }
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{% include "dispatcher.tmpliq" %}
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.clear:
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eor r6, r6
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vmov s16, r6
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vmov.f32 s17, s16
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vmov.f32 s18, s16
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vmov.f32 s19, s16
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vmov.f32 s20, s16
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vmov.f32 s21, s16
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vmov.f32 s22, s16
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vmov.f32 s23, s16
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vmov.f32 s24, s16
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vmov.f32 s25, s16
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vmov.f32 s26, s16
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vmov.f32 s27, s16
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vmov.f32 s28, s16
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vmov.f32 s29, s16
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vmov.f32 s30, s16
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vmov.f32 s31, s16
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b .non_linear_loop
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.add_mat_mul:
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// r3 <- k, r4 <- a, r5 <- b
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cmp r3, #0
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beq .non_linear_loop
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mov r1, r4 // packed A ptr
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pld [r3]
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pld [r5]
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.packed_packed:
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cmp r3, #4
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blt .packed_packed_loop_1
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.packed_packed_loop_4:
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// 1
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vldmia r1!, { s0, s1 }
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vldmia r5!, { s8, s9 }
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vmla.f32 s16, s0, s8
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vldmia r1!, { s2, s3 }
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vmla.f32 s17, s1, s8
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vldmia r5!, { s10, s11 }
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vmla.f32 s18, s2, s8
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vmla.f32 s19, s3, s8
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vmla.f32 s20, s0, s9
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vmla.f32 s21, s1, s9
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vmla.f32 s22, s2, s9
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vmla.f32 s23, s3, s9
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vldmia r1!, { s4-s7 }
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vmla.f32 s24, s0, s10
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vmla.f32 s25, s1, s10
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vmla.f32 s26, s2, s10
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vmla.f32 s27, s3, s10
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vldmia r5!, { s12-s15 }
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vmla.f32 s28, s0, s11
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vmla.f32 s29, s1, s11
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vmla.f32 s30, s2, s11
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vmla.f32 s31, s3, s11
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// 2
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vmla.f32 s16, s4, s12
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vmla.f32 s17, s5, s12
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vmla.f32 s18, s6, s12
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vmla.f32 s19, s7, s12
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vldmia r1!, { s0-s3 }
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vmla.f32 s20, s4, s13
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vmla.f32 s21, s5, s13
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vmla.f32 s22, s6, s13
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vmla.f32 s23, s7, s13
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vldmia r5!, { s8-s11 }
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vmla.f32 s24, s4, s14
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vmla.f32 s25, s5, s14
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vmla.f32 s26, s6, s14
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vmla.f32 s27, s7, s14
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vmla.f32 s28, s4, s15
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vmla.f32 s29, s5, s15
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vmla.f32 s30, s6, s15
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vmla.f32 s31, s7, s15
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// 3
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vmla.f32 s16, s0, s8
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vmla.f32 s17, s1, s8
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vmla.f32 s18, s2, s8
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vmla.f32 s19, s3, s8
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vldmia r1!, { s4-s7 }
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vmla.f32 s20, s0, s9
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vmla.f32 s21, s1, s9
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vmla.f32 s22, s2, s9
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vmla.f32 s23, s3, s9
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vldmia r5!, { s12-s15 }
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vmla.f32 s24, s0, s10
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vmla.f32 s25, s1, s10
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vmla.f32 s26, s2, s10
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vmla.f32 s27, s3, s10
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pld [r1]
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vmla.f32 s28, s0, s11
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vmla.f32 s29, s1, s11
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vmla.f32 s30, s2, s11
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vmla.f32 s31, s3, s11
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pld [r6]
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// 4
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vmla.f32 s16, s4, s12
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vmla.f32 s17, s5, s12
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vmla.f32 s18, s6, s12
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vmla.f32 s19, s7, s12
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vmla.f32 s20, s4, s13
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vmla.f32 s21, s5, s13
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vmla.f32 s22, s6, s13
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vmla.f32 s23, s7, s13
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vmla.f32 s24, s4, s14
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vmla.f32 s25, s5, s14
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vmla.f32 s26, s6, s14
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vmla.f32 s27, s7, s14
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vmla.f32 s28, s4, s15
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vmla.f32 s29, s5, s15
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vmla.f32 s30, s6, s15
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vmla.f32 s31, s7, s15
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sub r3, r3, #4
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cmp r3, #4
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bge .packed_packed_loop_4
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cmp r3, #0
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beq .non_linear_loop
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.packed_packed_loop_1:
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vldmia r1!, { s0, s1 }
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vldmia r5!, { s8, s9 }
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vmla.f32 s16, s0, s8
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vldmia r1!, { s2, s3 }
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vmla.f32 s17, s1, s8
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vldmia r5!, { s10, s11 }
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vmla.f32 s18, s2, s8
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vmla.f32 s19, s3, s8
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vmla.f32 s20, s0, s9
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vmla.f32 s21, s1, s9
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vmla.f32 s22, s2, s9
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vmla.f32 s23, s3, s9
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vmla.f32 s24, s0, s10
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vmla.f32 s25, s1, s10
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vmla.f32 s26, s2, s10
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vmla.f32 s27, s3, s10
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vmla.f32 s28, s0, s11
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vmla.f32 s29, s1, s11
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vmla.f32 s30, s2, s11
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vmla.f32 s31, s3, s11
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subs r3, r3, #1
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bne .packed_packed_loop_1
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b .non_linear_loop
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.add_unicast:
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{% for col in (0..3) %}
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mov r8, r3
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{% for reg in (0..3) %}
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vldr s0, [ r8 ]
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vadd.f32 s{{col|times:4|plus:reg|plus:16}}, s{{col|times:4|plus:reg|plus:16}}, s0
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{% if reg < 3 %}
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add r8, r8, r4
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{% endif %}
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{% endfor %}
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{% if col < 3 %}
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add r3, r3, r5
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{% endif %}
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{% endfor %}
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b .non_linear_loop
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.scalar_min:
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vmov s0, r3
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{% for reg in (16..31) %}
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vcmp.f32 s{{reg}}, s0
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vmrs apsr_nzcv, fpscr
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vmovge s{{reg}}, s0
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{% endfor %}
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b .non_linear_loop
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.scalar_max:
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vmov s0, r3
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{% for reg in (16..31) %}
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vcmp.f32 s{{reg}}, s0
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vmrs apsr_nzcv, fpscr
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vmovle s{{reg}}, s0
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{% endfor %}
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b .non_linear_loop
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.scalar_add:
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vmov s0, r3
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{% for s in (16..31) %}
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vadd.f32 s{{s}}, s{{s}}, s0
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{% endfor %}
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b .non_linear_loop
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.scalar_mul:
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vmov s0, r3
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{% for s in (16..31) %}
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vmul.f32 s{{s}}, s{{s}}, s0
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{% endfor %}
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b .non_linear_loop
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.scalar_sub:
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vmov s0, r3
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{% for s in (16..31) %}
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vsub.f32 s{{s}}, s0, s{{s}}
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{% endfor %}
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b .non_linear_loop
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.scalar_sub_flipped:
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vmov s0, r3
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{% for s in (16..31) %}
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vsub.f32 s{{s}}, s{{s}}, s0
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{% endfor %}
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b .non_linear_loop
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.per_row_min:
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vldm r3, {s0, s1, s2, s3}
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{% for row in (0..3) %}
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{% for col in (0..3) %}
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{%capture s%}s{{col|times:4|plus:row|plus:16}}{%endcapture%}
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vcmp.f32 {{s}}, s{{row}}
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vmrs apsr_nzcv, fpscr
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vmovge {{s}}, s{{row}}
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{% endfor %}
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{% endfor %}
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b .non_linear_loop
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.per_row_max:
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vldm r3, {s0, s1, s2, s3}
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{% for row in (0..3) %}
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{% for col in (0..3) %}
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{%capture s%}s{{col|times:4|plus:row|plus:16}}{%endcapture%}
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vcmp.f32 {{s}}, s{{row}}
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vmrs apsr_nzcv, fpscr
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vmovlt {{s}}, s{{row}}
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{% endfor %}
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{% endfor %}
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b .non_linear_loop
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.per_row_add:
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vldm r3, {s0, s1, s2, s3}
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{% for row in (0..3) %}
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{% for col in (0..3) %}
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vadd.f32 s{{col|times:4|plus:row|plus:16}}, s{{col|times:4|plus:row|plus:16}}, s{{row}}
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{% endfor %}
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{% endfor %}
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b .non_linear_loop
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.per_row_mul:
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vldm r3, {s0, s1, s2, s3}
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{% for row in (0..3) %}
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{% for col in (0..3) %}
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vmul.f32 s{{col|times:4|plus:row|plus:16}}, s{{col|times:4|plus:row|plus:16}}, s{{row}}
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{% endfor %}
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{% endfor %}
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b .non_linear_loop
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.per_row_sub:
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vldm r3, {s0, s1, s2, s3}
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{% for row in (0..3) %}
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{% for col in (0..3) %}
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vsub.f32 s{{col|times:4|plus:row|plus:16}}, s{{row}}, s{{col|times:4|plus:row|plus:16}}
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{% endfor %}
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{% endfor %}
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b .non_linear_loop
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.per_row_sub_flipped:
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vldm r3, {s0, s1, s2, s3}
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{% for row in (0..3) %}
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{% for col in (0..3) %}
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vsub.f32 s{{col|times:4|plus:row|plus:16}}, s{{col|times:4|plus:row|plus:16}}, s{{row}}
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{% endfor %}
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{% endfor %}
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b .non_linear_loop
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.per_col_min:
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vldm r3, {s0, s1, s2, s3}
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{% for row in (0..3) %}
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{% for col in (0..3) %}
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{%capture s%}s{{col|times:4|plus:row|plus:16}}{%endcapture%}
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vcmp.f32 {{s}}, s{{col}}
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vmrs apsr_nzcv, fpscr
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vmovge {{s}}, s{{col}}
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{% endfor %}
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{% endfor %}
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b .non_linear_loop
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.per_col_max:
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vldm r3, {s0, s1, s2, s3}
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{% for row in (0..3) %}
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{% for col in (0..3) %}
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{%capture s%}s{{col|times:4|plus:row|plus:16}}{%endcapture%}
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vcmp.f32 {{s}}, s{{col}}
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vmrs apsr_nzcv, fpscr
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vmovlt {{s}}, s{{col}}
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{% endfor %}
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{% endfor %}
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b .non_linear_loop
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.per_col_add:
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vldm r3, {s0, s1, s2, s3}
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{% for row in (0..3) %}
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{% for col in (0..3) %}
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vadd.f32 s{{col|times:4|plus:row|plus:16}}, s{{col|times:4|plus:row|plus:16}}, s{{col}}
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{% endfor %}
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{% endfor %}
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b .non_linear_loop
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.per_col_mul:
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vldm r3, {s0, s1, s2, s3}
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{% for row in (0..3) %}
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||||
{% for col in (0..3) %}
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vmul.f32 s{{col|times:4|plus:row|plus:16}}, s{{col|times:4|plus:row|plus:16}}, s{{col}}
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||||
{% endfor %}
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||||
{% endfor %}
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||||
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||||
b .non_linear_loop
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||||
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||||
.per_col_sub:
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||||
vldm r3, {s0, s1, s2, s3}
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||||
{% for row in (0..3) %}
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||||
{% for col in (0..3) %}
|
||||
vsub.f32 s{{col|times:4|plus:row|plus:16}}, s{{col}}, s{{col|times:4|plus:row|plus:16}}
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||||
{% endfor %}
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||||
{% endfor %}
|
||||
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||||
b .non_linear_loop
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||||
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||||
.per_col_sub_flipped:
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||||
vldm r3, {s0, s1, s2, s3}
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||||
{% for row in (0..3) %}
|
||||
{% for col in (0..3) %}
|
||||
vsub.f32 s{{col|times:4|plus:row|plus:16}}, s{{col|times:4|plus:row|plus:16}}, s{{col}}
|
||||
{% endfor %}
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||||
{% endfor %}
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||||
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||||
b .non_linear_loop
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||||
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||||
.add_row_col_products:
|
||||
vldmia r3!, { s0, s1 }
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vldmia r4!, { s8, s9 }
|
||||
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||||
vmla.f32 s16, s0, s8
|
||||
vldmia r3!, { s2, s3 }
|
||||
vmla.f32 s17, s1, s8
|
||||
vldmia r4!, { s10, s11 }
|
||||
vmla.f32 s18, s2, s8
|
||||
vmla.f32 s19, s3, s8
|
||||
|
||||
vmla.f32 s20, s0, s9
|
||||
vmla.f32 s21, s1, s9
|
||||
vmla.f32 s22, s2, s9
|
||||
vmla.f32 s23, s3, s9
|
||||
|
||||
vmla.f32 s24, s0, s10
|
||||
vmla.f32 s25, s1, s10
|
||||
vmla.f32 s26, s2, s10
|
||||
vmla.f32 s27, s3, s10
|
||||
|
||||
vmla.f32 s28, s0, s11
|
||||
vmla.f32 s29, s1, s11
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||||
vmla.f32 s30, s2, s11
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||||
vmla.f32 s31, s3, s11
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||||
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b .non_linear_loop
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||||
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||||
.store:
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||||
{% for col in (0..3) %}
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||||
mov r8, r3
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||||
{% for reg in (0..3) %}
|
||||
fsts s{{col|times:4|plus:reg|plus:16}}, [ r8 ]
|
||||
{% if reg < 3 %}
|
||||
add r8, r8, r4
|
||||
{% endif %}
|
||||
{% endfor %}
|
||||
{% if col < 3 %}
|
||||
add r3, r3, r5
|
||||
{% endif %}
|
||||
{% endfor %}
|
||||
|
||||
mov r0, #0
|
||||
b .return
|
||||
|
||||
|
||||
.q_scale:
|
||||
.q_shl:
|
||||
.q_shr:
|
||||
b .unsupported
|
||||
|
||||
.return:
|
||||
vpop { s16-s31 }
|
||||
pop { r4-r12 }
|
||||
|
||||
bx lr
|
||||
|
||||
Vendored
+32
@@ -0,0 +1,32 @@
|
||||
// vim: ft=arm
|
||||
|
||||
.non_linear:
|
||||
|
||||
.non_linear_loop_entry:
|
||||
sub r0, #20
|
||||
|
||||
.non_linear_loop:
|
||||
add r0, #20
|
||||
ldm r0, { r2, r3, r4, r5, r6 }
|
||||
|
||||
cmp r2, #{{ jump_table | size }}
|
||||
movgt r2, #{{ jump_table | size }}
|
||||
cmp r2, #0
|
||||
movlt r2, #{{ jump_table | size }}
|
||||
|
||||
add pc, pc, r2, LSL#2
|
||||
nop // pc in Rn above is start of the add instruction + 8, hence a nop is needed
|
||||
// This is A32 asm, for T32/Thump2 use nop.w and b.w to avoid problems.
|
||||
{% for j in jump_table %}
|
||||
b .{{j}}
|
||||
{% endfor %}
|
||||
b .unsupported
|
||||
|
||||
.unsupported:
|
||||
mov r0, #1
|
||||
b .return
|
||||
|
||||
.done:
|
||||
mov r0, #0
|
||||
b .return
|
||||
|
||||
Reference in New Issue
Block a user