// vim: ft=arm

// C tile regs: v16 to v31, (scratch)
// - x19-x29 to preserve (but x19, x28, x29 not used) 
// - d8..d15 to preserve
// - v16 to v31, no need to preserve

// v8 is used, d8 (lower half) must preserved
// v0-v7 (scratch registers)
//  packed A buffering (2x8 values): alternating v0, v1 with v2, v3
//  packed B buffering (2x8 values): alternating v4, v5 with v6, v7

.text
.align 4

.cpu generic+fp+simd
.global {{G}}arm64simd_mmm_f32_16x4_{{core}}_{{suffix}}
{{G}}arm64simd_mmm_f32_16x4_{{core}}_{{suffix}}:

    stp         x20, x21, [sp, #-16]!
    stp         x22, x23, [sp, #-16]!
    stp         x24, x25, [sp, #-16]!
    stp         x26, x27, [sp, #-16]!

    stp         d8, d9, [sp, #-16]!
    stp         d10, d11, [sp, #-16]!
    stp         d12, d13, [sp, #-16]!
    stp         d14, d15, [sp, #-16]!

{% include "dispatcher.j2" %}

.add_mat_mul:
    ldr         x2, [x0, #24]       // b
    ldp         x3, x1, [x0, #8]    // k, a

    cmp         x3, #0
    beq         .non_linear_loop

    ld1         { v0.4s, v1.4s, v2.4s, v3.4s }, [ x1 ], #64
    ld1         { v4.4s }, [ x2 ], #16

{% set packed_packed_loop1 %}
    {% if core == "a53" %}
        {% include "arm64simd_mmm_f32_16x4/packed_packed_loop1/cortex_a53.S.raw" %}
    {% else %}
        {% include "arm64simd_mmm_f32_16x4/packed_packed_loop1/naive.S.raw" %}
    {% endif %}
{% endset %}

{% set packed_packed_loop2 %}
    {% if core == "a55" %}
        {% include "arm64simd_mmm_f32_16x4/packed_packed_loop2/cortex_a55.S.raw" %}
    {% else %}
        {{ packed_packed_loop1 }}
        {{ packed_packed_loop1 }}
    {% endif %}
{% endset %}

    cmp         x3, #4
    blt         .packed_packed_loop_1

.p2align 4
.packed_packed_loop_4:
    {{ packed_packed_loop2 }}
    {{ packed_packed_loop2 }}

    sub x3, x3, #4
    cmp x3, #4
    bge .packed_packed_loop_4

    cmp x3, #0
    beq .non_linear_loop

.p2align 4
.packed_packed_loop_1:
    {{ packed_packed_loop1 }}
    subs        x3, x3, #1
    bne .packed_packed_loop_1

    b   .non_linear_loop

{% set from = 16 %}{% set to = 31 %}{% include "arm64simd_mmm_f32_scalars.j2" %}
{% set mr = 16 %}{% set from = 16 %}{% set to = 31 %}{% include "arm64simd_mmm_f32_per_rows.j2" %}
{% set mr = 16 %}{% set from = 16 %}{% set to = 31 %}{% include "arm64simd_mmm_f32_per_cols.j2" %}
{% set from = 16 %}{% set to = 31 %}{% include "arm64simd_mmm_load_tile.j2" %}

.add_unicast:
    ldp         x5, x6, [x0, #8]
    ldp         x7, x8, [x0, #24]

    {% for col in range(0, 4) %}
        mov x4, x5
        {% for reg in range(0, 4) %}
            {% for lane in range(0, 4) %}
                ld1 {v0.s}[{{lane}}], [ x4 ], x6
            {% endfor %}
            fadd v{{ col * 4 + 16 + reg }}.4s, v{{ col * 4 + 16 + reg }}.4s, v0.4s
        {% endfor %}
        add x5, x5, x7
    {% endfor %}

    b           .non_linear_loop

.add_row_col_products:
    ldr     x2, [x0, #8]
    ldr     x3, [x0, #16]

    ld1         { v0.4s, v1.4s, v2.4s, v3.4s }, [ x2 ]
    ld1         { v4.4s }, [ x3 ]

    fmla        v16.4s, v0.4s, v4.s[0]
    fmla        v17.4s, v1.4s, v4.s[0]
    fmla        v18.4s, v2.4s, v4.s[0]
    fmla        v19.4s, v3.4s, v4.s[0]
    fmla        v20.4s, v0.4s, v4.s[1]
    fmla        v21.4s, v1.4s, v4.s[1]
    fmla        v22.4s, v2.4s, v4.s[1]
    fmla        v23.4s, v3.4s, v4.s[1]

    fmla        v24.4s, v0.4s, v4.s[2]
    fmla        v25.4s, v1.4s, v4.s[2]
    fmla        v26.4s, v2.4s, v4.s[2]
    fmla        v27.4s, v3.4s, v4.s[2]
    fmla        v28.4s, v0.4s, v4.s[3]
    fmla        v29.4s, v1.4s, v4.s[3]
    fmla        v30.4s, v2.4s, v4.s[3]
    fmla        v31.4s, v3.4s, v4.s[3]

    b           .non_linear_loop

.store:
    ldp         x5, x6, [x0, #8]            // c base ptr, rsc
    ldp         x7, x8, [x0, #24]           // csc, item_size

    cmp         x6, #4
    bne           .store_strides_generic

    {% for col in range(0, 4) %}
        str q{{ col * 4 + 16 + 0 }}, [ x5 ]
        str q{{ col * 4 + 16 + 1 }}, [ x5, #16 ]
        str q{{ col * 4 + 16 + 2 }}, [ x5, #32 ]
        str q{{ col * 4 + 16 + 3 }}, [ x5, #48 ]
        add x5, x5, x7
    {% endfor %}

    b           .non_linear_loop

.store_strides_generic:

    {% for col in range(0, 4) %}
        mov x4, x5
        {% for reg in range(0, 4) %}
            {% for lane in range(0, 4) %}
                st1 { v{{ col * 4 + 16 + reg }}.s }[{{lane}}], [ x4 ], x6
            {% endfor %}
        {% endfor %}
        add x5, x5, x7
    {% endfor %}

    b           .non_linear_loop

.return:
    ldp         d14, d15, [sp], #16
    ldp         d12, d13, [sp], #16
    ldp         d10, d11, [sp], #16
    ldp         d8, d9, [sp], #16

    ldp         x26, x27, [sp], #16
    ldp         x24, x25, [sp], #16
    ldp         x22, x23, [sp], #16
    ldp         x20, x21, [sp], #16

    ret

